ARMv7: GICv2 driver can manage GICv1 with security extension

Some SoCs integrate a GIC in version 1 that is currently not supported
by the trusted firmware. This change hijacks GICv2 driver to handle the
GICv1 as GICv1 is compatible enough with GICv2 as far as the platform
does not attempt to play with virtualization support or some GICv2
specific power features.

Note that current trusted firmware does not use these GICv2 features
that are not available in GICv1 Security Extension.

Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179
Signed-off-by: Etienne Carriere <[email protected]>

diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 25296a63e4e66501b70837b395e1846ce897ace3..1d963baedfe289ccbc7c74c75667e0c174484d62 100644 (file)
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -167,7 +167,19 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
        gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
        gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT)
                                        & PIDR2_ARCH_REV_MASK;
-       assert(gic_version == ARCH_REV_GICV2);
+
+       /*
+        * GICv1 with security extension complies with trusted firmware
+        * GICv2 driver as far as virtualization and few tricky power
+        * features are not used. GICv2 features that are not supported
+        * by GICv1 with Security Extensions are:
+        * - virtual interrupt support.
+        * - wake up events.
+        * - writeable GIC state register (for power sequences)
+        * - interrupt priority drop.
+        * - interrupt signal bypass.
+        */
+       assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
 
        driver_data = plat_driver_data;
 

diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h
index 9e126a854b41e1c3630f0c8bb06b5d43b518fd40..67d4a28bad5762e1bd865220abf078dbe0e75c27 100644 (file)
--- a/include/drivers/arm/gic_common.h
+++ b/include/drivers/arm/gic_common.h
@@ -72,6 +72,8 @@
 #define ARCH_REV_GICV3         0x3
 /* GICv2 revision as reported by the PIDR2 register */
 #define ARCH_REV_GICV2         0x2
+/* GICv1 revision as reported by the PIDR2 register */
+#define ARCH_REV_GICV1         0x1
 
 #define IGROUPR_SHIFT          5
 #define ISENABLER_SHIFT                5